Seminars Fall 2000

Abstract:

During the past years, microwave-based oscillators were mostly designed using gallium arsenide material and different types of resonators. Since the advent of the silicon germanium process, which makes Ft corner frequencies of 75 GHz and higher possible, a lot of work has been done in this area. This presentation will focus on some of the RF-related considerations for designing oscillator RFICs for general purpose capable of operating up to microwave frequencies.

Abstract:

Very recently IBM has demonstrated the feasibility of a Nonvolatile RAM comprising a memory cell composed of a magnetic tunnel junction, for nonvolatile storage, in series with an FET, for selection/isolation (Cell structure is much like that of a DRAM). The semiconductor industry is carefully watching the development of this potentially revolutionary nonvolatile, high-density memory technology. The flow of current through a magnetic tunnel junction is regulated by setting the magnetic moment of a first ferromagnetic layer with respect to that of a second ferromagnetic layer. The macroscopic magnetic moment adjusts, on a molecular scale, the dominant electron spin of conduction electrons of the aforementioned first ferromagnetic layer. Electron spin controls electron transport across a tunnelling barrier and into a second ferromagnetic layer.

Abstract:

I will discuss the design and measurement (and re-design) of a SiGe BiCMOS track-and-hold for application in a disk drive read channel. The final design consumes 12.5mW from a 3V supply to give 6 bit accuracy at speeds well above 1GS/sec.

Abstract:

Fully integrated SiGe BiCMOS transmit and receive PLLs for 8B/10B coded 10Gb/s serial links operate with excellent jitter characteristics. The transmit PLL (TxPLL) provides a 12.5GHz clock with 0.4ps rms jitter synthesized from a ~195.3MHz reference. The receive PLL (RxPLL), which exhibits <0.56ps rms jitter generation, extracts a full rate clock and recovers data from a 12.5Gb/s input bit stream. The RxPLL operates error-free when tested with a 14km optical link test bench. The power consumption of the TxPLL and RxPLL cores at 3.3V is 270mW and 330mW, respectively.

Friday, November 17, 2000
Time: 2:30 PM, Room 414 Schapiro

Towards energy and delay reduction in VLSI interconnect - a theoretical approach

Abstract:

Technology scaling has dramatically changed the behavior of digital circuits. In deep sub-micron technologies transistors are extremely fast and what determines the operation of large digital circuits are the properties of the network interconnecting the individual building blocks. Data buses and clock distribution networks are the major bottlenecks in the design of future digital circuits. The issues of power consumption and delay in deep sub-micron data buses will be addressed. New techniques based on a distributed bus model, for reducing the power and increasing the speed of the buses will be described.

Tuesday, October 31, 2000
Time: 12:45 PM, Room 414 Schapiro

Towards an Energy Complexity of Computation

Abstract:

Energy consumption is becoming a critical complexity parameter along with time (delay) in the design and optimization of algorithms at both the hardware and software levels. In this talk, I propose that a new complexity measure including energy $E$ and time $t$ in the form of the expression $E\times t^2$ be used as the measure of the efficiency of a computation. I prove that the metric is optimal. As an example, a new result concerning the optimal length of a pipeline is derived.

Short CV: Alain J. Martin is a Professor of Computer Science at the California Institute of Technology. He is a graduate from the Institut National Polytechnique de Grenoble, France. His research interests include concurrent and distributed computing, and VLSI design. His research group is well known for their pioneering work in the area of asynchronous VLSI and asynchronous microprocessor architectures. In particular, they designed the world-first asynchronous microprocessor in 1989.

Friday, October 27, 2000
Time: 2:30 PM, Room 233 Mudd

Dynamic Biasing Sample and Hold Amplifiers for High Resolution Mixed Mode Reflective Liquid Crystal Displays

Abstract:

Emerging High-Resolution Reflective Liquid Crystal Displays (RLCD) back planes define new IC technology requirements and circuit developments. Image contrast, brightness, frame rates and colour depth call for fast high dynamic range data converter arrays. Philips's mixed mode RLCD back planes could be seen as a dynamic analog memory cells structure with a word length equal to the horizontal image resolution. During a frame, the entire memory is sequentially (row by row) addressed, every cell being updated with a potential proportional to an associated pixel brightness level. A column based 8-bit pulse-width modulation digital to analog converter generates the voltage level stored into the memory cell. At the end of the conversion time, a sample and hold circuit "stores" the conversion result in a column capacitance. For an UXGA (1600x1200 pixels) resolution display, a number of 1600 sample and hold amplifiers are implemented. A dynamic biasing technique has been used a to achieve low power consumption, high bandwidth and minimal silicon area requirements. Design trade-offs are explained in this presentation.

Friday, October 13, 2000
Time: 2:30 PM, Room 414 CEPSR Schapiro

Framework for One-Bit Nonlinear Sigma-Delta Modulation

Abstract:

Sigma-Delta modulation is a technique used to perform high resolution A/D and D/A conversion while being tolerant to analog circuit imperfections. This is achieved by integrating a coarse resolution quantizer into a linear feedback loop and by sampling the input at a higher rate then the Nyquist frequency (oversampling). The tolerance to circuit imperfections is maximized when a one-bit quantizer is used. However, research on one-bit schemes is currently reaching saturation, yielding more and more to investments in multi-bit or multi-quantizer schemes with special circuit design to reduce the sensitivity to circuit imperfections.

In this talk, we propose to revisit one-bit quantization as some new approach has been recently introduced by mathematicians (Princeton University and University of South Carolina). The main consequences of this approach are as follows:

1 - It is shown in the one-bit case that the actual tradeoff between the oversampling and the global conversion resolution is not what was predicted by the classical noise-shaping model (n+1/2 bits/octave). New analytical tools are provided, that explain the actual tradeoff (n bits/octave only).

2 - With the same analytical tools, the new approach formalizes a framework under which nonlinear operations can be integrated. Nonlinear Sigma-Delta schemes carrying new properties have resulted from this framework, including schemes that recover the "missing" 1/2 bit/octave and schemes that are analytically and globally stable at arbitrary orders.

Friday, October 6, 2000
Time: 2:30 PM, Room 414 CEPSR Schapiro

Active LC Filters on Silicon

Abstract:

The advent of highly integrated wireless communication transceivers provides potential applications for integrated active LC filters. Compared to the continuous-time filters not using inductors, active LC filters can achieve larger dynamic range with similar power consumption. Integrated active LC filters are not simply copies of their discrete counterparts. The difficulty of integration mostly results from two problems. One is that the reactive components integrated on silicon are very lossy and have significant parasitics associated with the silicon substrate. This makes it extremely challenging to design an integrated active LC filter with desired exact frequency response. The other problem is how to make active LC filters automatically tunable. Tuning an active LC filter in the GHz range automatically is a design challenge. In this talk, the above issues will be addressed, and two prototype chips, one using Lucent's 0.25 um BiCMOS and the other using IBM's 0.5 um SiGe BiCMOS, will be described.

Friday, September 22, 2000
Time: 2:00 PM, Room 415 Schapiro Building

Digitally Corrected Delta-Sigma Data Converters

Abstract:

Delta-sigma data converters are among the key components of modern digital communication systems. While they are relatively insensitive to analog component accuracy, there are very important situations where their design goals cannot be achieved without additional calibration or correction procedures. These may occur for the cascade or MASH structures, where high resolution is achieved by cancelling a large quantization noise using both analog and digital components, requiring extreme accuracy from the former ones, or in the design of multibit-quantizer converters which need digital-to-analog converters with impractical linearity requirements.

Some recent results will described for the algorithms and implementation of both digital and analog correction techniques in the design of high-performance delta-sigma A/D and D/A converters. The proposed techniques will be illustrated with practical and numerical examples.