Seminars Spring 2000

Friday, April 28, 2000
Time: 2:00 PM, Room 415 Schapiro Building

Analog Cell Development for Low Power Wireless Applications

Abstract:

Mixed-Signal Analog integrated circuits for portable wireless applications are constantly increasing in complexity. Handset manufacturers hope to reduce battery cell usage in order to reduce weight, cost and size. Lower supply voltage requirement becomes a major driver for creative analog designers. Besides reduced voltage supply, power consumption is the other paradigm. Internet wireless services, video and other fast transmission rates call for pipelined and higher speed/resolution converters without the luxury of adding extra power. Also, audio Codecs become more sophisticated with 16 bit true resolution, stereo drivers and 4 ohm loads to support MPEG3 and Hi-Fi performance.

In addition to the complexity increase mentioned above, another facet of portable wireless applications is the so-called "system on a chip". It is becoming more evident that a single-chip phone is not only feasible but essential for the same kind of reasons viz. weight, cost, size and power. However, analog integration on a digital CMOS process comes with its own problems and challenges ^ especially at supply voltages approaching 1.1 volts in processes that have Leff of around 0.1 microns.

Friday, April 21, 2000
Time: 2:00 PM, Room 415 Schapiro Building

Generation of Equivalent Circuits from Physics-Based Device Simulation

Abstract:

Device modeling faces conflicting requirements of accuracy, efficiency and development time. We will present a new technique to directly generate equivalent-circuit models from device simulation. A circuit block is generated for each region of the device (e.g., neutral and depletion regions). All the circuit elements have a clear physical interpretation. The method promises model generation times comparable with those of black-box and physics-based device models. New device structures and physical phenomena (e.g., optoelectronic effects) are easily included. Applications to one-dimensional pn junctions and bipolar transistors will be presented.

Friday, April 14, 2000
Time: 2:00 PM, Room 415 Schapiro Building

Asynchronous Interlocked Pipelined CMOS Circuits Operating at 3.3 - 4.5 GHz

Abstract:

An asynchronous circuit technique suitable for multi - GHz operation using interlocked local clocks will be described. These circuits drive a path through a typical 64b multiplier stage at 3.3 - 4.5 GHz in 0.18um 1.5V CMOS technology.

Friday, March 24, 2000
Time: 2:00 PM, Room 415 Schapiro Building

IF Sampling in Wireless Transceivers

Abstract:

The main motivation for digitizing the IF signals in wireless transceivers is the promise for increased robustness, added system flexibility, and better overall reliability.

However, a careful analysis shows that the actual incorporation of IF sampling into an efficient and inexpensive transceiver architecture is not straightforward, as serious practical difficulties need to be overcome.

The most critical issue is the design of the analog front end. In addition to performing conventional functions, this circuit is required to suppress the aliasing of blockers. A new undersampling approach will be discussed. The presentation will include a short tutorial review of wireless transceivers.

Friday, March 10, 2000
Time: 2:00 PM, Room 415 Schapiro Building

A Single IF Receiver Architecture using a Complex Sigma-Delta Modulator

Abstract:

In the growing market for portable communications, it is becoming more important to design high performance transceivers which consume little power. Currently, many architectures are exploited to give the maximum dynamic range while running off a 1V battery. This makes it challenging to design components such as A/D converters which may be required to have 12-bit resolution.

This talk discusses a new A/D converter called a Complex Bandpass SD Modulator, suitable for a Single-IF receiver architecture. This modulator is based on existing bandpass SD Modulator structures, and was designed to give roughly double the bandwidth performance of existing state of the art. Two versions of this modulator were designed and fabricated as switched-C circuits in a 0.8um BiCMOS technology, and the results are presented. The maximum SNDR of these modulators was 48dB with a bandwidth of 10kHz and a sampling rate of 4MHz wth a power dissipation of 160mW. The maximum operating frequency was found to be approximately 45MHz.

This modulator was also tested with a suitable analog front-end operating at an RF of 1.9GHz and an IF of 60MHz. Results are presented for demodulated GMSK data (similar to GSM) for this receiver. This is meant to show the feasibility of using this type of SD modulator in a radio receiver.

Tuesday, January 25, 2000
Time: 11:00 AM, Room 415 Schapiro Building

Analysis, Simulation and Applications of Passive Devices over the Si Substrate

Abstract:

On-chip passive devices, such as spiral inductors and transformers, have the potential to improve the performance of key RF building blocks. However, their use not only necessitates proper modeling of magnetic effects, but also parasitic substrate impedance and coupling. An accurate and efficient technique to model the device over a wide frequency range will be presented. To aid the designer in using the technique, a custom CAD tool ASITIC (Analysis and Simulation of Inductors and Transformers for ICs) will be presented. This tool provides the RF designer a user friendly graphical environment where the key geometric parameters of inductors or transformers can be optimized. By working with the entire RF chip layout, the tool also allows the user to investigate the effects of magnetic and substrate coupling across the entire chip.

These general techniques can also be applied to other VLSI circuits. The design of high speed analog and digital circuits requires careful modeling of on-chip interconnect parasitics. At lower frequencies, only the effects of capacitance is important whereas at higher frequencies the effects of both capacitive and inductive coupling must be considered. This is also of paramount importance in mixed signal circuits where substrate coupling from noisy digital circuits into sensitive analog circuits can greatly impact performance. Two example applications of on-chip passive devices, a voltage controlled oscillator (VCO) and a power amplifier (PA) will be presented. In these applications the performance of the passive devices plays a critical role in the overall system performance.