Seminars Spring 2001

Abstract:

The mission of the VLSI Design and Architecture department at IBM Research is to contribute VLSI design, microarchitecture, and performance expertise into leading edge microprocessor designs and to explore new microarchitectures, system designs and organizations, code optimization, circuits, and design tools and methodologies. I will give a brief overview of ongoing projects in our department and illustrate how we are able to drive innovative ideas from Research into real products. I will then spend most of the time summarizing IBM Research's Global Technology Outlook.

Abstract:

A movement away from specialized bipolar process technology to pure digital CMOS technology has characterized the last fifteen years of analog IC design. Merged BiCMOS technology has not become a mainstream option as a result of the high incremental process costs for the BiCMOS devices. Challenging the analog designer is the fact that maximum operating voltages have fallen concurrently with each smaller geometry generation of core CMOS transistors. Designers have moved from a 10V environment to a 3.3V environment with surprisingly little trouble. The start of the new century brings new challenges as the maximum operating voltage of 0.15u to 0.1u process technology has dramatically reduced to 1.5V - 1.0V. At the same time, modular BiCMOS is evolving. The costs of these technologies, as a percentage of the total wafer cost, have declined significantly. Modular SiGe bipolar devices now challenge the performance space once occupied only by GaAs. Copper interconnect systems, low k dielectrics and modular substrate engineering offer, for the first time, high Q passive inductors on chip.

In this talk, we will examine the current process technology options available to the analog designer and use our foggy crystal ball to predict whether core digital CMOS or modular BiCMOS will emerge as the mainstream choice for mixed-signal and RF chip designs in the early part of this.

Abstract:

This talk will start with a brief overview of the challenges in embedded SoC design. We will then describe some work with Jason Fritts to evaluate programmable architectures for single-chip video processors. We performed a large number of experiments using the MediaBench benchmarks to evaluate VLIW and superscalar processors' performance on media processing. These experiments helped us determine the effectiveness of a number of architectural features for media processing.

Abstract:

A MOSFET-C channel selection filter for a direct conversion WCDMA receiver is presented. This 5th order elliptic filter achieves 1.8 dBV in-band IIP3, +27.8 dBV out-of-band IIP3, +93.8 dBV out-of-band IIP2, 46.7 uV rms input-referred noise, and dissipates 6.2 mW from a 2.7 V supply; the on-chip continuous automatic tuning system dissipates 4.1 mW.

Abstract:

In the decade before World War II, Black, Bode, and Nyquist put the concept of feedback on a firm theoretical base that made highly reliable, practical applications possible. The impact of feedback is far broader than how it transformed electrical engineering, both in what could be accomplished and in how EEs are educated. Feedback is ubiquitous. It has influenced virtually every area of intellectual endeavor; it is integral to the physical realization of nearly everything that comprises today's information society. This talk begins to address several questions concerning feedback. Among them are:

1. What were the earliest uses of feedback and why didn't these lead to a more general usage?
2. What was the reaction to Black's amplifier proposal?
3. What are some of the implications of the concept of feedback?

Abstract:

The field of radio frequency integrated circuit (RFIC) design is currently enjoying a renaissance, driven by the explosive growth in wireless applications.Because of this sudden and unexpected growth, there has been a frenzied scramble to train RF engineers to meet the high demand. A major challenge in this task is that RF design is multidisciplinary in nature, requiring knowledge of communications and signal propagation theory, transceiver architectures, and circuit design. To address the education and research issues associated with the demand,this talk will present an intensive first-year graduate course designed specifically to produce competent RFIC designers in one year along with onging research conducted in the Cornell Broadband Communications Research Lab (CBCRL).

Abstract:

This work presents a novel technique for the design of continuous time analog filters with high dynamic range and low power dissipation. The essence of the method is to break up the required dynamic range of the filter in smaller ranges, and utilize separate filters in each one of them. This is done in such a way that the output is not disturbed whenever a different filter takes over. Very serious power dissipation and chip area savings will be shown to result from this technique.

Abstract:

Over the last twenty years numerous studies dealing with Gm-(grounded)C biquad filter design have been published. While each of these fine publications provides a "good set" of filter topologies none of them seems to clearly identify the "complete set".

In this talk I will derive the "complete set" of practical HP and notch biquad topologies. The result of this derivation is quite unexpected: there are only five distinct topologies (two notches and three HP). Two of them require precise Gm matching while the other three do not.

Abstract:

A quadrature "splitter" assumes a reference clock at frequency f_in, f_min <= f_in <= f_max. The output is two equal-amplitude signals c(t) and s(t) both periodic with frequency f_in but spaced exactly one-quarter of a period apart: i.e., c(t) = s(t+T/4), T=1/f_in. Such a quadrature pair can be used, for example, to generate single sideband modulation. The suppression of the undesired sideband depends directly on the accuracy of the quadrature signals. We describe such a scheme, which injection-locks a cascade of ring oscillators in such a manner as to generate extremely accurate quadrature for f_in in excess of 2GHz with a tuning range of at least 100MHz. Our scheme places no requirements on the waveform of the reference clock. Simulation and preliminary experimental data confirm our claims of quadrature accuracy on the order of 0.1 degrees of phase. When used for a SSB modulator, this implies suppression of the undesired sideband by at least 50dB.

Injection-locking is related to but distinct from phase locking. In particular, there is no requirement for a low-pass "loop" filter, hence no issue of loop stability. A brief discussion of the theory of injection-locking will be presented.

Abstract:

Logic verification continues to be considered one of CAD`s most difficult problems, highlighted with the discovery of the Pentium bug dilemma. This talk reviews certain current innovations addressing such problems. A new method will be discussed, based on what has become known as Recursive Learning Technique. This proposed technique has its cornerstone in Boolean implication techniques -- proven most powerful when traditional approaches such as OBDD fail. In fact, Recursive Learning was the first to verify the ISCAS benchmark circuits -- discovering some bugs in the process. This work has won the l996 IEEE Transactions on CAD/Best Paper Award, patented that same year. Several CAD companies currently implement this technique in their tool.

Abstract:

The problem of the evaluation of phase noise in integrated LC-oscillators is discussed. We show that is possible to obtain a simple expression for the output phase noise that takes into account the circuit non-linearities, avoiding the use of "black box" simulators. Using simple physical arguments, supported by experimental data, we show that some upconversion mechanism usually neglected, as those arising from indirect stability or from AM/PM conversion, may be instead dominant and invalidate the noise vs. power trade-off. These considerations will be applied to the design of two circuits: a 2.5 GHz bipolar oscillator with an Automatic Amplitude Control loop, and a 5 GHz CMOS oscillator for Bluetooth standard.