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Spring 2013 Seminars
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Title : Millimeter-wave Radiometers and THz Imaging Arrays (Distinguished Lecture Co-sponsored by IEEE NY EDS/SSCS)
Speaker: Prof. Gabriel M. Rebeiz,
University of California, San Diego
Date: Friday, February 1st, 2:15pm-3:15pm, 633 Mudd
Title : The Journey to High Speed and High Resolution SAR ADCs -- an engineering case study
Speaker: Dr. Junhua Shen,
Analog Devices
Date: Friday, March 8th, 2:30pm-3:30pm, Interschool Lab (750 Schapiro)
Title : Low-Noise CMOS IC for Radiation Detectors in Space, Physics, and Medical Applications
Speaker: Dr. Shaorui Li,
BNL
Date: Friday, April 5th, 2:15pm-3:15pm, 633 Mudd
Title : Continuous-time Delta Sigma Data Converters with Reduced Clock Jitter Sensitivity and Enhanced Linearity (Co-sponsored by IEEE NY EDS/SSCS)
Speaker: Prof. Shanthi Pavan,
IIT-Madras
Date: Friday, April 12th, 2:30pm-3:30pm, Interschool Lab (750 Schapiro/CEPSR)
Title : 30 Years of TI's DSP: What's Next?
Speaker: Dr. Fernando Mujica,
Director, System Architectures Lab, Texas Instruments, Inc.
Date: Friday, April 17th, 2:00pm-3:00pm, Interschool Lab (750 Schapiro)
Title : Transconductance linearization techniques and autonomic biasing for low phase noise VCOs
Speaker: Dr. Bodhisatwa Sadhu,
IBM T. J. Watson Research Center
Date: Friday, April 19th, 2:30pm-3:30pm, 414 Schapiro/CEPSR
Title : Utilizing Physics for Energy Efficient Computation
Speaker: Prof. Jennifer Hasler,
GaTech
Date: Thursday, May 16th, 2:00pm-3:00pm, 414 CEPSR
Title : SDR Transmitters: Analog or Digital? (Distinguished Lecture Co-sponsored by IEEE NY EDS/SSCS)
Speaker: Dr. Jan Craninckx,
IMEC (Leuven, Belgium)
Date: Friday, May 31st, 2:00pm-3:00pm, 633 Mudd
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Prof. Gabriel M. Rebeiz,
University of California San Diego
Date:
Friday, February 1st, 2:15pm-3:15pm
Location:
633 Mudd
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Millimeter-wave Radiometers and THz Imaging Arrays (Distinguished Lecture Co-sponsored by IEEE NY EDS/SSCS)
Abstract:
The fundamental concepts of radiometers (passive imaging) and imaging arrays (active imaging) will be covered. This includes the definition of responsivity, noise-equivalent power (NEP), Dicke switching and 1/f noise, integration time and NEDT, coupling efficiency especially when using on-chip antennas, coupling efficiency to a plane wave or to an imaging system, will be first presented. The talk will then cover some of the latest chips developed by academia and industry at 94-160 GHz (radiometers), and 160-800 GHz detectors and active imaging arrays using SiGe, CMOS and advanced CMOS SOI nodes.
Biography:
Prof. Gabriel Rebeiz is the Wireless Communications Industry Chair Professor at the University of California, San Diego. He is an IEEE Fellow, an NSF Presidential Young Investigator, an URSI Koga Gold Medal Recipient, IEEE MTT 2003 Distinguished Young Engineer, and is the recipient of the IEEE MTT 2000 Microwave Prize, the IEEE MTT 2010 Distinguished Educator Award and the IEEE Antennas and Propagation 2011 John D. Kraus Antenna Award. He is also the recipient of the 1998 Amoco Teaching Award given to the best undergraduate teacher at the University of Michigan, and the 2008 Jacobs ECE Teacher of the Year Award at UCSD. His group has lead the development of complex RFICs for phased array applications from X-band to W-band, culminating recently in wafer-scale integration with high efficiency on-chip antennas. His phased array work is now used by most companies developing complex communication and radar systems. He has graduated 50 PhD students and 16 post-doctoral fellows, and currently leads a group of 20 PhD students in mm-wave RFIC, planar mm-wave antennas and terahertz systems, microwave circuits, RF MEMS, tunable networks, and is the Director of the UCSD/DARPA Center on RF MEMS Reliability and Design Fundamentals.
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Dr. Junhua Shen,
Analog Devices
Date:
Friday, March 8th, 2:30pm-3:30pm
Location:
Interschool Lab (750 Schapiro)
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The journey to high speed and high resolution SAR ADCs -- an engineering case study
Abstract:
Analog-to-digital converters are ubiquitous in today's information era, from cell phones, cameras, to cars and industrial equipment. Successive approximation registers (SAR) ADCs are unique among various types of ADCs in that they are power efficient, small and have very low latency. On the other hand, SAR ADCs are inherently slower than some other types of ADCs, like pipeline and flash, due to its sequential bit-trial nature for each conversion. As such, SAR ADCs mainly find applications in lower than 10Msps space. This talk will be divided into two sections. In the first section, an 80Msps, 14-bit SAR ADC will be presented, with highlights of several ideas which enabled the high speed and high resolution operation. In the second section, the design will be used as an engineering case study to show the technical journey of pushing the state-of-the-art of SAR ADCs.
Biography:
Junhua Shen received his B.Eng. from Zhejiang University in Hangzhou, China, in 2002. He continued his study at The Chinese University of Hong Kong and Columbia University, where he earned his M.Phil. and Ph.D. respectively. His master's thesis focused on high image-rejection continuous-time sigma-delta modulator, while his PhD research was mainly on ultra-low-voltage and low-power pipelined ADCs. In Feb. 2010, he joined Analog Devices in Wilmington, MA as a senior design engineer, where he has been working on high speed, high resolution SAR ADCs and digital imaging related products. His interests are in analog-to-digital converters and system level solutions that involve ADCs.
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Dr. Shaorui Li,
BNL
Date:
Friday, April 5th, 2:15pm-3:15pm
Location:
633 Mudd
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Low-Noise CMOS IC for Radiation Detectors in Space, Physics, and Medical Applications
Abstract:
Radiation sensors detect and convert radiation of interest (e.g. charged particles, neutrons, X- and gamma-rays) into electric charge. Reading out from radiation sensors requires highly specialized electronics. In this talk, the low-noise design techniques and circuits adopted in state-of-the-art CMOS ICs for radiation detectors are presented. Examples in space, physics, and medical applications are given, explaining some special issues on CMOS devices including lifetime and radiation-induced leakage.
Biography:
Dr. Shaorui Li received the PhD degree in 2005 in electrical engineering from Columbia University. She joined Agere Systems (formerly Bell Labs Microelectronics) in 2005 designing RF and mixed-signal ICs for 3G/LTE wireless transceivers. Since 2009, she joined Brookhaven National Laboratory developing low-noise CMOS ICs for radiation detectors. She holds three patents and has authored over 20 technical papers including one book chapter. Her main interests are in the area of analog and mixed-signal integrated circuits.
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Prof. Shanthi Pavan,
IIT-Madras
Date:
Friday, April 12th, 2:30pm-3:30pm
Location:
Interschool Lab (750 Schapiro)
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Continuous-time Delta Sigma Data Converters with Reduced Clock Jitter Sensitivity and Enhanced Linearity (Co-sponsored by IEEE NY EDS/SSCS)
Abstract:
Clock jitter degrades the performance of a continuous-time delta sigma converter. A common approach to addressing this issue is the use of a switched capacitor feedback DAC. Unfortunately, using such a DAC can severely degrade the modulator's linearity. In this talk, I will describe the Switched-Capacitor Return-to-Zero DAC, which is a recent technique that improves jitter immunity and modulator linearity at the same time.
A modulator test chip designed and fabricated in a 0.18um CMOS process achieves 87dB dynamic range in a 2MHz bandwidth.
Biography:
Shanthi Pavan obtained the B.Tech degree in Electronics and Communication Eng. from the Indian Institute of Technology, Madras in 1995 and the M.S and Sc.D degrees from Columbia University, New York in 1997 and 1999 respectively. After working in industry for a few years, he moved to the Indian Institute of Technology-Madras, where he is now a Professor of Electrical Engineering. His research interests are in the areas of high speed analog circuit design, sensing and signal processing.
Dr.Pavan is the recipient of the 2012 Shanti Swarup Bhatnagar Award in Engineering Sciences from the Government. of India, the IEEE Circuits and Systems Society Darlington Best Paper Award (2009), the Swarnajayanthi Fellowship (2010, from the Government of India) , the Young Faculty Recognition Award from IIT Madras (2009, for excellence in teaching) , the Technomentor Award from the India Semiconductor Association (2010) and the Young Engineer Award from the Indian National Academy of Engineering (2006). He is the Deputy Editor in Chief of the IEEE Transactions on Circuits and Systems: Part I - Regular Papers and serves on the Data Converter Committee of the International Solid State Circuits Conference (ISSCC).
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Dr. Fernando Mujica,
Director, System Architectures Lab, Texas Instruments, Inc.
Date:
Wednesday, April 17th, 2:00pm-3:00pm
Location:
Interschool Lab (750 Schapiro)
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30 Years of TI's DSP: What's Next?
Abstract:
Independent of who is telling the story, DSP is a relatively new concept. For example, at Texas Instruments, we are celebrating the 30th anniversary of the programmable DSP this year. But that birth 30 years ago was the result of many discoveries made in academic research labs. But, in this talk, we will only focus on that part of the DSP story in which we played a prominent role. We will start the story with our first programmable DSP, the TMS32010 and tell the story of how DSP moved from being magic to being an permanent part of our lives. We will finish the talk with a few predictions of what the future might hold for these amazing processors which take the theories of signal processing and make their magic much more than an allusion.
Biography:
Fernando Mujica is Director, System Architectures Lab of the Systems and Applications Research and Design Center at Texas Instruments, Inc. He is responsible for the technical direction of the lab and for maintaining a pipeline of projects in support of businesses across TI. Fernando and the researchers in his organization work on a wide range of technologies including signal processing techniques to enhance analog solutions, signal processing VLSI architectures and massively parallel multi-core programmable co-processors. Fernando's research interests are in the general area of signal processing. He has been granted seventeen US patents and has more in the pipeline. Fernando holds a Ph.D. degree in electrical engineering from the Georgia Institute of Technology, Atlanta, GA, and Electronic Engineering and Magister in Electronic Engineering degrees from Universidad Simon Bolivar, Caracas, Venezuela.
In his spare time Fernando enjoys playing tennis, photography and motor sports. He is a club-racer and high-performance driving instructor for the BMW Car Club of America. He also instructs for Apex Driving Academy and Street Survival, a teenager driving program. He is married to Gayle and they have three children: Elena, Sofia and Andy.
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Dr. Bodhisatwa Sadhu,
IBM T.J. Watson Research Center
Date:
Wednesday, April 19th, 2:30pm-3:30pm
Location:
414 Schapiro/CEPSR
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Transconductance linearization techniques and autonomic biasing for low phase noise VCOs
Abstract:
Phase noise in CMOS LC VCOs is fundamentally limited by the oscillation amplitude and the inherent device noise. This talk will describe a new approach based on transconductance linearization of the active devices that increases the signal swing while reducing the active device noise contribution in LC VCOs providing excellent phase noise performance.
A prototype 25GHz VCO based on this linearization approach is integrated in a dual-path PLL and achieves superior performance compared to the state of the art. The design is implemented in 32nm SOI CMOS technology and achieves a phase noise of ?130dBc/Hz at a 10MHz offset from a 22GHz carrier. A new layout approach for switched capacitor arrays enables a wide tuning range of 23%.
Also, a digitally assisted autonomic biasing technique is implemented in the PLL to provide a phase noise and power optimized VCO bias across frequency and process. Measurement results to indicate the efficacy of the autonomic biasing scheme will be presented.
Biography:
Bodhisatwa Sadhu is currently a Post-doctoral Researcher at IBM T.J. Watson Research Center, NY. He received his B.E.(Hons.) degree in Electrical and Electronics Engineering from Birla Institute of Technology and Science, Pilani, in 2007 and his Ph.D. degree in Electrical Engineering from the University of Minnesota, Minneapolis, in 2012. For his Ph.D., he worked on wideband circuits and architectures for software defined radio applications.
In 2007, he was with Broadcom Corporation, Bangalore, where he worked on system integration and verification of ethernet switch SoCs. In Fall-2010 and Summer-2011, he was with the Mixed Signal Communications IC Design Group, IBM T.J. Watson Research Center where he worked on the analysis and design of low phase noise frequency synthesizers for 60GHz and 94GHz applications. Dr. Sadhu is the recipient of the University of Minnesota Graduate School Fellowship, 2007, 3M Science and Technology Fellowship, 2009 and the University of Minnesota Doctoral Dissertation Fellowship, 2011.
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Prof. Jennifer Hasler,
Georgia Tech
Date:
Thursday, May 16th, 2:00pm-3:00pm
Location:
414 Schapiro/CEPSR
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Utilizing Physics for Energy Efficient Computation
Abstract:
Increasing demand for portable electronics results without increasing battery capability results in an ever increasing demand for increased computational resources in a constant power environment. We effectively want to utilize the physics of computing systems more efficiently; the question is how to engineer such systems. These techniques are even more critical given the saturation of computational energy efficiency of digital multiply accumulate structures, the key component for high-performance computing. One approach would be to consider using analog techniques. These approaches are fueled by recent advances in programmable and configurable large-scale analog circuits and systems enabling a typical factor of 1000 improvement in computational power (Energy) efficiency over their digital counterparts. Large-Scale Field Programmable Analog Arrays (FPAA), devices analogous to FPGAs, enable configurable analog approaches. The ability for non-volatile analog memory fuels all other innovations. We will overview a few examples in this area including speech, vision, and sensor interfaces, as well as the CAD tools to enable design of these systems. Another approach is to take inspiration from neurobiological systems to further improve the resulting energy efficiency. These silicon systems mimic extremely energy efficient neural computing structures, potentially both for solving engineering applications as well as understanding neural computation. These neuromorphic systems should enable additional increases in energy efficiency; recent research has demonstrated some of these examples. Scaling of energy efficiency, performance, and size impact the application space of Neuromorphic systems. Therefore, research in analog signal processing, neuromorphic engineering, and programmable / configurable analog approaches provide opportunities for continued energy efficiency scaling.
Biography:
Jennifer Hasler is a Professor in the School of Electrical and Computer Engineering at Georgia Institute of Technology. Dr. Hasler received her M.S. and B.S.E. in Electrical Engineering from Arizona State University in 1991, and received her Ph.D. From California Institute of Technology in Computation and Neural Systems in 1997. Dr. Hasler received the NSF CAREER Award in 2001, and the ONR YIP award in 2002. Dr. Hasler received the Paul Raphorst Best Paper Award, IEEE Electron Devices Society, 1997, IEEE CICC best paper award, 2005, Best student paper award, IEEE Ultrasound Symposium, 2006, IEEE ISCAS Sensors best paper award, 2005, and best demonstration paper, ISCAS 2010. Dr. Hasler is a Senior Member of the IEEE.
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Dr. Jan Craninckx,
IMEC (Leuven, Belgium)
Date:
Friday, May 31st, 2:00pm-3:00pm
Location:
633 Mudd
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SDR Transmitters: Analog or Digital? (Distinguished Lecture Co-sponsored by IEEE NY EDS/SSCS)
Abstract:
Flexibility and reconfigurability are the new keywords in RF design, several applications require transceivers operating in different modes to fulfill market requirements. Recent research has shown two very different trends. Classical analog-inspired architectures focus on performance numbers that are on par with dedicated radios, using circuits and techniques that offer programmability at low (or no) cost. Digital-intensive approaches offer flexibility for free, but even more important are not limited by the analog performance bottlenecks in new technology nodes.
This presentation will give an overview of several examples in this field, with a focus on their respective possibilities and limitations. The analog voltage-sampling transmitter is a key enabler for the tough out-of-band noise requirements in cellular systems. Extension with harmonic-rejection techniques allow is also the tackle the linearity counter-IM3 issue in LTE systems. On the digital side, both polar and cartesian (I/Q) direct digital RF modulators (DDRM) are published, that take the functionality of an RF DAC. FIR-based filtering is proposed to lower RX-band noise below the quantization noise, and a Doherty architecture tackles the efficiency for high output powers.
Biography:
Jan Craninckx obtained his Ms. and Ph.D. degree in microelectronics summa cum laude from the ESAT-MICAS laboratories of the Katholieke Universiteit Leuven in 1992 and 1997, respectively. His Ph.D. work was on the design of low-phase noise CMOS integrated VCOs and synthesizers.
From 1997 till 2002 he worked with Alcatel Microelectronics (later part of STMicroelectronics) as a senior RF engineer on the integration of RF transceivers for GSM, DECT, Bluetooth and WLAN.
In 2002 he joined IMEC (Leuven, Belgium), where he currently is the senior principal scientist of the analog wireless research group. His research focuses on the design of RF transceiver front-ends for software defined radio (SDR) systems, covering all aspects of RF, analog and data converter design.
Dr. Craninckx has authored and co-authored more than 100 papers and several book chapters, and is the inventor of 10 patents. He is a member of the Technical Program Committee for the several conferences, was the chair of the SSCS Benelux chapter (2006-2011), and is an Associate Editor of the JSSC.
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